Wednesday, September 15 - Morning
8:40 a.m. – 10:20 a.m.
WA1.1 Analysis and Design of Monolithic, High PSR, Linear Regulators for SoC Applications, Vishal Gupta, Gabriel A. Rincon-Mora, Prasun Raha*, Georgia Institute of Technology, Atlanta, GA and * Texas Instruments
WA1.2 High-gain high-speed operational amplifier in digital 120nm CMOS, Franz Schlögl, Horst Dietrich, Horst Zimmermann, Vienna University of Technology, Vienna, Austria
WA1.3 A Compensation Technique for Transistor Mismatch in Current Mirrors, Sripriya R. Bandi and P.R. Mukund, Rochester Institute of Technology, Rochester, NY
WA1.4 A New Design for Built-In Self-Test of 5GHz Low Noise Amplifiers, Jee-Youl Ryu and Bruce C. Kim, Arizona State University, Tempe, AZ
WB1.1 Decoupling Capacitors for Power Distribution Systems with Multiple Power Supply Voltages, Mikhail Popovich and Eby G. Friedman, University of Rochester, Rochester, NY
WB1.2 Low Power Repeaters Driving RC Interconnects with Delay and Bandwidth Constraints, Guoqing Chen and Eby G. Friedman, University of Rochester, Rochester, NY
WB1.3 Global Interconnect Optimization with Simultaneous Macrocell Placement and Repeater Insertion, Yuantao Peng and Xun Liu, NCStateUniversity, Raleigh, NC
WB1.4 Mutual Inductance Modeling for Multiple RLC Interconnects with Application to Shield Insertion, Junmou Zhang and Eby G. Friedman, University of Rochester, Rochester, NY
10:20 a.m. BREAK
10:40 a.m. – 11:55 a.m.
WA2.1 SoC Design of Remote Terminals for Wireless Telemetry System, Wonjae Lee, Sangyun Hwang* Minho Kwon, Seongjoo Lee* Jaeseok Kim, YonseiUniversity, Seoul, Korea and *Samsung Electronics, Suwon, Korea
WA2.2 An Improved Delay-Hopped Transmitted-Reference Ultra Wideband Architecture, Xiaomin Chen and Sayfe Kiaei, Arizona State University, Tempe, AZ
WB2.1 VLSI Design and Analysis of a Critical-band Transform Processor for Speech Recognition, Chao Wang, Yit-Chow Tong and Yu Shao, Nanyang Technological University, Singapore
WB2.2 An Application-Specific Processor Hard Macro for Real-time Control, Xiaofeng Wu, Vassilios Chouliaras and Roger Goodall, Loughborough University, Loughborough, United Kingdom
WB2.3 FPGA-efficient Phase-to-I/Q Architecture, Ireneusz Janiszewski, Hermann Meuth, and Bernhard Hoppe, University of Applied Sciences Darmstadt, Darmstadt, Germany
11:55 p.m. - 1:10 p.m. LUNCH
Wednesday, September 15 - Afternoon
Who is in the Driver Seat for SoC Technology: EDA or Design?
Panelists: Ali Sheikoleslami (Moderator), Professor, Univ. of Toronto
Mike Keating, VP, Synopsys Henry Chang, VP, Cadence Jagdish Pathak, President, Submicron Circuits Michael Green, Professor, UC Irvine Bob Pitts, Platform Manager, TI
2:40 p.m. BREAK
2:50pm – 4:50 p.m.
WA3.1 A Novel Half-Rate Architecture for High-Speed Clock and Data Recovery, Qiurong He and Milton Feng, The University of Illinois at Urbana-Champaign, Urbana, IL
WA3.2 A 3.8GHz Channel-Select Filter Using 0.18µm CMOS, Jiandong Ge and Anh Dinh, University of Saskatchewan, Saskatoon, Canada
WA3.3 Optimum Design and Trade-offs for a Triple-band LNA for GSM, WCDMA and GPS Applications, Nazanin Darbanian, Sayfe Kiaei*, and Shahin Farahani, Freescale Semiconductor, Inc., and *Arizona State University, Chandler, AZ
WB3.1 (Invited Paper) Extended Dynamic Voltage Scaling for Low Power Design, Bo Zhai, David T. Blaauw, Dennis Sylvester, and Krisztian Flautner*, University of Michigan, Ann Arbor, MI and *ARM Ltd., Cambridge, United Kingdom
WB3.2 ChipPower : An Architecture-Level Leakage Simulator, Yuh-Fang Tsai, Ananth Hegde Ankadi, N. Vijaykrishnan, Mary Jane Irwin, and Theo Theocharides, Penn State University, State College, PA
WB3.3 CoolPression -- A Hybrid Significance Compression Technique for Reducing Energy in Caches, Mrinmoy Ghosh, Weidong Shi, and Hsien-Hsin S. Lee, Georgia Institute of Technology, Atlanta, GA