Sunday, Sept. 12, 2004
Chair: Suhwan Kim, Seoul National University, Korea

(select one)

Analog, Mixed-Signal and RF Design for SOC Applications

8:00 a.m. – 11:40 a.m.
Trade-Offs in RF Analog Circuit Design for SOC Applications
S. Farahani, Freescale Semiconductor Inc., S. Kiaei, Arizona State University, N. Darbanian, Freescale Semiconductor Inc., M. H. Smith, Intel Corporation, and A. Hietala, RF Micro Devices

The exploding applications of wireless communications have increased the need for high performance and low cost RF and analog circuits. The main challenge in the development of RF and analog circuits is the trade-off between the linearity, noise, area, and power consumption of each block. The biasing point contributes directly to the circuit performance and power consumption. A proper quiescent point can reduce the sensitivity to the process and temperature variation. Also the power consumption needs to be minimized in order to maximize the battery life. The goal is to meet the selectivity and sensitivity requirements with minimum power dissipation and area.

In this half day tutorial, a detailed practical study of the effect of different circuit parameters including biasing and the device geometries on the performance of the circuit is provided. The selected building blocks for this presentation are Low Noise Amplifiers (LNAs), mixers, filters, and frequency synthesizers. Several fabricated design examples are provided and will be discussed.

SoC Design Methodology in Deep Submicron Technology

8:00 a.m. – 11:40 a.m.
SoC Design Methodology: A Practical Approach
A. Jain, Texas Instruments, USA and A. Saha, Texas Instruments, India

Today’s deep submicron semiconductor technology has enabled integration of multi-milliongates into a single chip, called System-On-a-Chip (SoC). All these systems require integrationof multiple standard of-the-shelf components and/or custom chips that include RISC processorand/or DSP cores along with memory, peripherals, bus bridges, and user defined logic. Thisintegration has resulted in several challenges for the design teams, in terms of increased designcomplexity, functional verification, timing closure, physical design, signal integrity, reliability,manufacturing test, and package design. The single largest barrier to successful creation andproduction of such SoCs’ is not in the manufacturing facility but the productivity of the designteams. Typically, it takes a team of 12-15 engineers approximately 10-12 months tosuccessfully complete a medium size design. On the contrary, the market and business needsare driving for a much shorter design cycle time of 4-6 months to meet the time to marketwindow and rely on smaller design teams of 6-8 engineers to be competitive. Hence, thebiggest challenge for SoC to be successful is to at least double the productivity of designengineers. This can be accomplished by having a robust design methodology that is based ondesign reuse and automation.This tutorial will discuss a design methodology that is based on experience of presenterswith successfully designing several digital dominated Communications Processors, VOP, andDSL SoC designs in Broadband Communications Design Centers at Texas Instruments. It willprovide a complete breadth of digital chip design. In addition, it will cover some issues relatedto mixed signal SoC. Design tradeoffs will be discussed to handle the SoC complexity andmeet the time-to-market demand. We will also review different methodologies that arefollowed in the industry to design these chips. Following topics will be covered with examples to explain design challenges and their solutions.

  • Design Planning
  • Functional Verification
  • Design For Test (DFT)
  • Synthesis, Floor-planning, and STA
  • Design Closure
  • Manufacturing Tests
  • Future Challenges


11:50 a.m. – 1:00 p.m. – Lunch on your own


(select two)

Analog, Mixed-Signal and RF Design for SOC Applications

1:00 p.m. – 2:50 p.m.
Substrate Coupling Noise and its Reduction through Early Design Planning in Mixed-Signal SoCs
M. Chrzanowska-Jeske and G. Blakiewicz, Pennsylvania State University

A mixed-signal SOC, integrating analog, digital and possibly RF circuitry on a single chip, offers many advantages: improved circuit performance, reduced system size, and lower fabrication cost. However, it challenges designers with increased power dissipation, signal integrity problems, testing complexity, and process integration issues.

Substrate-coupling noise is becoming one of the major factors limiting the performanceof (MS-SOC) designs. Analog and digital cores are integrated on a common substrate and performance of analog blocks can experience considerable degradation due to digital switching. When device dimensions shrink beyond a certain limit, the isolation of reverse-biased pn-junctions is not sufficient enough to suppress substrate noise. The semiconductor industry uses two major types of substrate to fabricate integrated circuits: lightly-doped and heavily-doped (with a thin epitaxial layer on top). Many mixed-signal SOCs are fabricated using lightly-doped substrate, where the amount of substrate coupling strongly depends on module spacing. Therefore, its impact should be considered in the early design planning stage to avoid costly corrections at later stages of design.

The aim of this tutorial is to present challenges associated with substrate coupling noise in sub-micron mixed-signal SOCs, and provide an updated overview on the main methodologies, techniques, and tools to reduce the effect of substrate noise. Based on identification of important substrate noise sources and layout-aware characterization of sensitive circuits and coupling mechanisms, an extensive discussion of reduction techniques possible at various stages of system design is presented. Advantages and limitations of new approaches to early physical design planning and its influence on faster and more reliable design convergence will be discussed.

This tutorial discusses: types of substrates; substrate noise sources and their characterization and modeling; noise sensitive circuits and their modeling and characterization; noise attenuation with distance and its relation to layout and floorplanning for lightly-doped substrates, noise reduction techniques (wells, trenches and guard ring), classical methods for noise simulation and modeling, and new approaches to noise reduction during early design planning.

The target audience includes (1) analog/mixed-signal and digital VLSI/SOC system and circuit designers and design project managers (2) physical implementation methodologists and CAD system integrators (3) EDA researchers and developers who are facing the problems of power and substrate noise limited MS SOC designs.

3:00 p.m.– 4:50 p.m.
A 243-GHz Ft and 208-GHz Fmax, 90-nm SOI CMOS SoC Technology with Low-Power Millimeter-Wave Digital and RF Circuit Capability
N. Zamdmer, J. Kim, R. Trzcinski, J. Plouchart, S. Narasimha, IBM

SOI CMOS technology offers low parasitic junction capacitance, and therefore provides speed and power enhancements to digital applications compared to bulk CMOS. It is also emerging as a good candidate for high performanceSoC, with integratable RF circuits that operate beyond 30-GHz already demonstrated at the 130-nm technology node. The digital aspects of the base 90-nm SOI technology were previously reported. This tutorial presents the RF performance of this technology, and shows that the capabilities of CMOS technology are expanding into the millimeter-wave regime.

SoC Design Methodology in Deep Submicron Technology

1:00 p.m. – 2:50 p.m.
Heterogenenous Modeling of SoCs with System C using Multi-MOC Kernel of System C
H. D. Patel and S. K. Shukla, Virginia Tech

SystemC has been positioned over the past years as a suitable system level design language and framework for designers to build models of working systems (such as embedded software/hardware systems, or a system-on-chip). However, on close encounter with SystemC, it becomes clear that the current SystemC standard only implements a discrete-event (DE) simulation semantics in its kernel, and hence any other model of computation which best expresses a component will be forced to be mapped and simulated with a DE semantics, resulting in unnecessary delta-cycles, leading to inefficient simulation.

The solution to this inadequacy is providing SystemC with an ability to model various components of a system in the most appropriate Model of Computation (MoC) for the component’s functionality.  For example, if a system-on-chip design for a digital camera consists of a DSP processor, a microcontroller, and Analog-Digital and Digital to Analog converters, and some glue logics, each of these components may be suitable for modeling in different MoC domains. For example, the DSP component may be best modeled with a Synchronous Data Flow model, while the microcontroller may be modeled with precise clock accurate discrete-event computation models. We call a framework that allows such multi-MoC modeling and simulation a multi-MoC framework.  Ptolemy II is such a multi-MoC framework that   requires the user to build the components in Java, using some characteristics of the target MoC domain, and then placing the components in the appropriate domain under the control of a domain director, which schedules and guides the simulation of these components, and helps the components communicate according to domain specific communication rules.  The facilities of multi-MoC modeling provided by this framework are designed in a way, so that the multi-MoC designs can be faithfully modeled and simulated. However, as the frameworks vary in the granularity of the MoC domains supported, one can imagine that the fidelity of the framework varies.

Recently we have extended the SystemC framework by adjoining distinct kernels to the DE kernel of SystemC so that CSP (Communicating Sequential Processes), FSM (Finite State Machine), and SDF (Synchronous Data Flow) MoC specific kernels allow designers to model components whose functionalities are most appropriately modeled in these MoC domains.

In this tutorial, we will cover the basic ideas of Models of Computation for SOC modeling, need for multi-MoC modeling framework for simulation efficiency and ease of modeling, followed by an introduction to the multi-MoC extension of SystemC through examples and explanation of how the modeling and simulation works.

3:00 p.m. – 4:50 p.m.
High-Performance CMOS Circuits for Sub-90nm Design
Steven K. Hsu, Intel Corporation

High-end servers, desktop platforms, and mobile/handheld platforms have introduced new challenges in advanced CMOS circuit design: (i) high frequencies in power constrained designs, (ii) increasing transistor leakage, and (iii) reverse scaling of interconnects.  Circuit design techniques to combat (i) increasing switching and standby/active leakage power consumption while maintaining high performance, (ii) degradation of leakage tolerance/robustness in register files/arrays, and (iii) worsening global on-chip interconnect scaling are presented.  This tutorial examines these primary CMOS circuit design challenges and the associated key paradigm shifts that will be required in future microprocessors and DSPs.


5:00 p.m. – 6:30 p.m. – Opening Reception