Conference Highlights

Distinguished Speakers:  (click on name ore scroll down for more information)

SOCC 2004 -  Santa Clara, CA


Paul E. Jacobs

Executive Vice President and President,
QUALCOMM Wireless & Internet Group



“Beyond Voice: The Third Generation of Wireless”


Kiyoo Itoh

Fellow, Hitachi Ltd



“Reviews and Prospects of Low-voltage RAM Circuits”


James D. Meindl

Director, Microsystems Research Center, and Professor, Microsystems, Georgia Institute of Technology



“The Interconnect Era of ASIC/SOC Technology”


Michael Riordan

Adjunct Professor, University of California Santa Cruz





Jürgen Koehl

Distinguished Engineer, IBM Technology Group



“IBM ASIC Design TAT Reduction”

Panel Discussions, reception, vendor fair:

The conference will feature a panel discussion about the question
“Who is in the Driver Seat for SoC Technology: EDA or Design?”
Chair will be Sreedhar Natarajan, MoSyS

On tuesday night there will be a reception and a vendor fair in conjunction with the International Cadence User Conference at the Westin hotel across the street.

Corporate Sponsors:

Several corporate sponsors of our conference will be present with tabletop displays. For more information, proceed to the Sponsors page.

Tutorial Workshops:

Like every year, there will be several half-day tutorials.


Keynote Speaker

Dr. Paul E. Jacobs
Executive Vice President and President,
QUALCOMM Wireless & Internet Group

“Beyond Voice: The Third Generation of Wireless”

Dr. Paul E. Jacobs is group president of QUALCOMM Wireless & Internet Group. In this role, Jacobs oversees QUALCOMM Internet Services, QUALCOMM Technology Licensing, QUALCOMM Wireless Business Solutions and QUALCOMM Digital Media. Dr. Jacobs is also responsible for overseeing corporate marketing, QUALCOMM ventures, standards organization, as well as corporate support engineering.

Previously, Dr. Jacobs served as executive vice president of QUALCOMM. He was responsible for leading QUALCOMM Consumer Products, QUALCOMM's CDMA handset business, from 1995 through its sale to Kyocera Wireless in 2000. In 2001, Jacobs helped conceive the Binary Runtime Environment for Wireless™ (BREW™) applications platform, now part of QUALCOMM Internet Services.

Dr. Jacobs has been involved in establishing and/or managing joint ventures with Sony, Microsoft and Ford, which enabled QUALCOMM's entry into consumer electronics manufacturing, enterprise software and consumer telematics, respectively. He served as CEO of QCP Incorporated, a wholly owned subsidiary of QUALCOMM, providing contracted design and distribution services to Kyocera Wireless Corporation

From 1990 through 1995, Dr. Jacobs held positions in QUALCOMM's engineering organization. He led the technical team that developed the variable rate 8 kbps speech codec for CDMA, which led to one of over 25 patents belonging to Jacobs in the area of wireless technology and devices. Dr. Jacobs also led QUALCOMM's efforts to standardize the speech codec. He also ran QUALCOMM's wireless local loop development, which spurred the 13 kbps speech codec that provided wire line quality, and the CDMA data and fax service.

Dr. Jacobs received his Ph.D. in electrical engineering from the University of California, Berkeley in 1989. He serves on the boards of the La Jolla Music Society, the Museum of Contemporary Art San Diego and the Salk Institute for Biological Studies. He is a member of the Advisory Board of the University of California at Berkeley College of Engineering, and Chairman of the Advisory Board of UCSD Jacobs School of Engineering.

    ABSTRACT -- The key drivers of the wireless industry have changed as each generation of technology has provided new capabilities.  With the rollout of 3G CDMA (third generation code division multiple access) around the world, the industry has moved from selling commoditized voice services to offering differentiated services enabled by high bandwidth connectivity and handheld devices with significant processing power, increased memory, high resolution displays and cameras, position location and embedded multimedia.  This talk will examine the technology roadmaps which are combining to enable this transition and showcase some of the services that are being offered successfully worldwide.

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Plenary Speakers

Dr. Kiyoo Itoh
Hitachi Ltd.

“Reviews and Prospects of Low-voltage RAM Circuits”

Dr. Kiyoo Itoh received his B.S. and Ph.D. degrees in electrical engineering from Tohoku University, Japan, in 1963 and 1976, respectively.  He is currently one of four Fellows at Hitachi Ltd. He was a Visiting MacKay Lecturer at the University of California, Berkeley, in 1994, a visiting professor at the University of Waterloo in 1995, and a consulting professor at Stanford University from 2000 to 2001.

Since 1972 he has led RAM circuit technology at Hitachi Ltd. He was the lead designer of the first prototype for eight generations of Hitachi DRAMs ranging from 4Kb to 64Mb. As early as 1988, as a pioneer, he started developing low-power/low-voltage CMOS circuits focusing on subthreshold current reduction.

He holds more than 200 patents in Japan, and more than 160 patents in the U.S., including seminal RAM circuits such as the folded bit line, on-chip voltage-down converter, and gate-source self-backbiasing schemes to reduce subthreshold current. He has authored and co-authored three books on memory designs, and more than 120 papers in IEEE journals and conference proceedings.

He served on the IEEE Solid-State Circuits Award Committee from1998 to 2000. He was a member of the IEEE Fellow Committee from1999 to 2002, and an elected AdCom member of IEEE Solid-State Circuits Society from 2001 to 2003. He is a Distinguished Lecturer, a member of the Award Committee, and a member of the Nomination Committee of the IEEE Solid-State Circuits Society.

Dr. Itoh has won many honors, including the IEEE Paul Rappaport Award in1984, the Best Paper Award of ESSCIRC90, and the 1993 IEEE Solid-State Circuits Award. He is an IEEE Fellow. In Japan, Dr. Itoh’s awards include the Commendation by the Minister of State for Science and Technology (Person of Scientific and Technological Merits) in 1997, and a National Medal of Honor with Purple Ribbon in 2000.

    ABSTRACT -- First, trends in RAM chip developments are reviewed, and challenges to low-voltage RAMs are clarified in terms of three design issues; maintenance of cell signal charge, reductions of leakage (gate tunnel current and subthreshold current), and reductions of variations of threshold voltage(Vt) and Vt-mismatch between paired MOSFETs.

    Second, there are general discussions on low-voltage RAM circuits, focusing on the above three issues. The discussions include comparisons of signal charge and soft-error rates between DRAM and SRAM cells, leakage characteristics and leakage reduction circuits for both standby and active modes, and Vt-variation and Vt-mismatch that cause a degraded signal charge and speed variations of peripheral circuits.

    Third, state-of-the-art RAM cells and peripheral circuits are discussed in detail, mainly focusing on subthreshold-current reductions for active mode. Fortunately, RAM peripheral circuits are in favor of the reduction, which differs from random logic gates.

    Finally, my perspectives for low-voltage RAMs are given. They include comparisons between various embedded RAM cells, such as the 1-T cell and gain cells, in terms of cell size, low-voltage operation capability, and necessary refresh times. Emerging RAM cells such as non-volatile RAMs, and devices and circuits for low-voltage peripheral circuits of the future are also discussed from the point of view of a circuit designer.

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Prof. James D. Meindl
Director, Microsystems Research Center, and Professor, Microsystems
Georgia Institute of Technology

“The Interconnect Era of ASIC/SOC Technology”

James Meindl is the director of the Joseph M. Pettit Microsystems Research Center, and has been the Joseph M. Pettit Chair Professor of Microsystems at Georgia Institute of Technology since 1993.

Professor Meindl was born in Pittsburgh, PA, and received his Ph.D., M.S., and B.S.,  in 1958, 1956, and 1955, respectively, in Electrical Engineering at Carnegie Institute of Technology (Carnegie-Mellon University). Prior to his tenure at Georgia Tech, he served as senior vice president for academic affairs and provost of Rensselaer Polytechnic Institute from 1986 to 1993.

He was with Stanford University from 1967 to 1986 as the John M. Fluke professor of  electrical engineering, associate dean for research in the School of Engineering, founding director of the Center for Integrated Systems, director of the Electronics Laboratories and founding director of the Integrated Circuits Laboratory.

Prof. Meindl is the author of several books and over 300 technical papers on ultra large scale integration, integrated electronics, and medical electronics He was the founding editor of IEEE Journal of Solid-State Circuits from1966-1971

Prof. Meindl is a life-fellow of the IEEE, a fellow of the American Association for the Advancement of Science, and a member of the National Academy of Engineering, the American Academy of Arts and Sciences, and the National Academy of Engineering and its Academic Advisory Board.

He has received numerous awards, among them the 1999 SIA University Research Award, the 1997 Hamerschlag Distinguished Alumnus Award from Carnegie Mellon University, and the 1991 Benjamin Garver Lamme Medal from ASEE.  He was the recipient of the 1990 IEEE Education Medal "for establishment of a pioneering academic program for the fabrication and application of integrated circuits" and the recipient of the 1989 IEEE Solid-State Circuits Medal for contributions to solid-state circuits and solid-state circuit technology.

At the 1988 IEEE International Solid-State Circuits Conference, he received the Beatrice K. Winner Award.  In 1980 he was the recipient of the IEEE Electron Devices Society's J.J. Ebers Award for his contributions to the field of medical electronics and for his research and teaching in solid-state electronics.

From 1970 through 1978 Dr. Meindl and his students received five outstanding paper awards at IEEE International Solid-State Circuits Conferences, along with one received at the 1985 IEEE VLSI Multilevel Interconnections Conference.

His major contributions have been new medical instruments enabled by custom integrated electronics, projections and codification of the hierarchy of physical limits on integrated electronics, and leadership in creation of academic environments promoting high quality teaching and research.

    ABSTRACT -- Interconnections have replaced transistors as the principal determinants of the performance, energy dissipation and cost of gigascale silicon chips. 
    For current state-of-the-art 100 nm generation technology:

    • the 5 ps intrinsic switching delay of a MOSFET is virtually negligible compared with the 30 ps latency of a “benchmark” one millimeter long Cu-lo k interconnect;
    • the 2 fJ energy dissipation associated with a binary transition of a minimum size transistor is virtually negligible compared with the 10 pJ energy dissipated during a transition of the benchmark interconnect; and
    • the number of masking levels required for FEOL fabrication of transistors ranges between 8-20 while the number of levels necessary for BEOL fabrication of interconnects ranges between 18-24.

    This “tyranny of interconnects” escalates rapidly for future generations of silicon technology. Consequently, further advances in the technology will necessarily be “interconnect-centric.”  New structures such as carbon nanotubes must be utilized for local interconnects to avoid impending increases in the resistivity of copper interconnects due to severe surface and grain boundary scattering in sub-50 nm generations.   Photonic interconnects must be extended to the chip itself particularly to enhance bandwidth through the use of wavelength division multiplexing and to extend clock frequencies to the 50 GHz range using mode-locked lasers.  New low cost, high density wafer level batch-fabricated “Sea of Leads” electrical and optical input/output interconnects are needed to support 300 ampere supply currents and 50 Tb/s input/output bandwidths for gigascale chips. In addition, thermal input/output interconnects are forecast in order to remove 300 W of chip power dissipation from a compact package.
    Finally, new interconnect-centric circuit configurations, such as a 10 GHz standing wave oscillator with distributed gain; system microarchitectures emphasizing symmetrical multiprocessors; and interconnect-awaresoftware are essential to “keep interconnects short.” In essence, to fulfill the needs of interconnect era gigascale chips a five-level hierarchy of novel fundamental, material, device, circuit and system level interconnect-centric solutions must be provided.

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Banquet Speaker

Dr. Michael Riordan
Adjunct Professor, UC Santa Cruz

Dr. Michael Riordan is Adjunct Professor of Physics at UC Santa Cruz and a Lecturer in the History of Philosophy of Science Program at Stanford University.

After earning his Ph.D. from the Massachusetts Institute of Technology in 1973, he did experimental research in particle physics at MIT, the University of Rochester, and the Stanford Linear Accelerator Center before turning to the history of physics in the late 1980s.

He has written or coauthored highly acclaimed general books on the discovery of quarks (The Hunting of the Quark: A True Story of Modern Physics), on dark matter and the structure of the Universe, and on the invention of the transistor (Crystal Fire: The Birth of the Information Age). He recently won the prestigious American Institute of Physics Andrew Gemant Award for his efforts in communicating physics through his books, articles and television programs.

Dr. Riordan leads a group of historians and physicists studying the history of the Superconducting Super Collider, which was terminated by Congress in 1993. In connection with this project, he received a Guggenheim Fellowship in 1999-2000. He originated and teaches a physics department course on the history of 20th century physics titled "The Quantum Century."

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Luncheon Speaker

Dr. Jürgen Koehl
Distinguished Engineer,
IBM Technology Group

“IBM ASIC Design TAT Reduction”

Dr. Jürgen Koehl studied Mathematics in Bonn and Paris. He received his Ph.D. in mathematics from Bonn University in 1987. Prior to joining the IBM development lab in Boeblingen, Germany in 1989, he was a member of the VLSI research team at the Institute for Discrete Mathematics in Bonn, Germany.

After joining IBM, he continued to work with this team and jointly implemented one of the first timing driven design systems which was used for the first IBM CMOS S/390 processors in the early 90's. He continued to contribute to the development of the IBM ASIC methodology by developing in-place timing optimization techniques, clock skew scheduling and timing driven routing solutions. From 2001 to 2003 Jürgen Koehl was on assignment to Burlington, Vermont to lead the world wide ASIC design turn-around-time reduction for IBM’s ASIC Design centers. Currently he is a Distinguished Engineer in the IBM ASIC Design Center in Boeblingen, Germany.  Dr. Koehl is a senior member of the IEEE.

    ABSTRACT -- A key factor in the time-to-market for an ASIC design is turnaround time (TAT). Because of the ever-increasing complexity of ASIC designs, a 30% reduction in TAT simply keeps the development time at a constant level in the evolution from one technology node to the next. More time must be shaved from TAT to reduce the overall development time. The base for this improvement was a detailed analysis of the major contributors to design TAT. The improvement presented in this talk, include algorithmic improvements, new sign off criteria, a higher degree of automation and more powerful IT equipment.

    Putting all these measures in place, IBM has reduced the time required to process the production netlist by 60% in a two-year window. These TAT reductions and the higher complexity of the 130 nm technologies result in a triple productivity improvement from one technology node to the next. It will be shown that the main contributors to design TAT changed as a result of this work. The placement and timing closure step with ideal clocks, that dominated the TAT in 2001 is by now no longer the bottleneck and the focus shifted to the percentage of TAT spent on post routing timing and noise closure. The improvements put in place to address this part of the process will be outlined.

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